Digital communication of information from a source to a receiver may be done source synchronously. Source synchronous communication involves a clock signal from the source (“forwarded clock signal”) being sent in parallel with other information from the source. Such other information may include data or control information, where control information includes address information.
There are different types of source synchronous communication, which may depend on the application. For example, in source synchronous communication between integrated circuits, frequency of the source clock signal from a source integrated circuit may be known a priori by a receiving integrated circuit. An example of this type of source synchronous interface may be found in communication with synchronous memory, where a data or source clock signal is sent in parallel with data/control information.
However, for example, in source synchronous communication in networking or telecommunication, such as between a transmitting device and a receiving device, frequency of a source clock signal may not be known by the receiving device. Furthermore, due to differences in signal propagation delays, there may be skew between information communicated in parallel with the source clock signal. For example, data on one channel may be askew from data on another channel.
Accordingly, programmable logic devices (“PLDs”), to provide multi-purpose use, have been made with two separate source synchronous interfaces. A Field Programmable Gate Array (“FPGA”) is one type of PLD where two or more different types of source synchronous interfaces may be co-located on an integrated circuit. An FPGA typically includes an array of configurable logic blocks (“CLBs”), programmable input/output blocks (“IOBs”) and other programmable resources. The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (“bitstream”) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured.
In conventional FPGAs having two different source synchronous interfaces for example, one interface is for local integrated circuit-to-integrated circuit communication, such as between a memory and an FPGA, and another interface is for more remote communication, such as an FPGA used for computer network or telecommunication network communication. Moreover, separate source synchronous interfaces for different applications may be formed in processors, Application Specific Integrated Circuits and Application Specific Standard Products, among other integrated circuits, and is not limited to PLDs. However, having at least two separate interfaces for different source synchronous applications increases pin count, as well as consumes significant semiconductor die area.
Accordingly, it would be desirable and useful to provide a multi-purpose source synchronous interface that may be used for either as a memory or a networking source synchronous interface.